FPGA-Based Reconfigurable Convolutional Neural Network Accelerator Using Sparse and Convolutional Optimization

Nowadays, the data flow architecture is considered as a general solution for acceleration of deep neural network (DNN) because its higher parallelism. However, conventional DNN accelerator offers only restricted flexibility diverse models. In order to overcome this, reconfigurable convolutional (RCNN) accelerator, i.e., one DNN, required be developed over field-programmable gate array (FPGA) platform. this paper, sparse optimization weight (SOW) and (CO) are proposed improve performances RCNN accelerator. The combination SOW CO used optimize feature map sizes accelerator; therefore, hardware resources consumed by minimized in FPGA. RCNN-SOW-CO analyzed means size, sparseness input (IFM), parameter proportion, block random access memory (BRAM), digital signal processing (DSP) elements, look-up tables (LUTs), slices, delay, power, accuracy. An existing architectures OIDSCNN, LP-CNN, DPR-NN justify efficiency RCNN-SOW-CO. LUT with Alexnet designed Zynq-7020 5150, which less than OIDSCNN DPR-NN.